Template:Hardware acceleration: Difference between revisions

Revision as of 09:05, 31 August 2022

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v t e Hardware acceleration
Theory	Universal Turing machine Parallel computing Distributed computing
Applications	GPU GPGPU DirectX Audio Digital signal processing Hardware random number generation Artificial intelligence Cryptography TLS Machine vision Custom hardware attack scrypt Networking Data
Implementations	High-level synthesis C to HDL FPGA ASIC CPLD System on a chip Network on a chip
Architectures	Data flow Transport triggered Multicore Manycore Heterogeneous In-memory computing Systolic array Neuromorphic
Related	Programmable logic Processor design chronology Digital electronics Virtualization Hardware emulation Logic synthesis Embedded systems

Revision as of 14:29, 23 May 2022 (view source) alpha>Sarika (Created page with "{{Navbox \| name = Hardware acceleration \| title = Hardware acceleration \| listclass = hlist \| state = {{{state\|autocollapse}}} \| group1 = Models of computa...") ← Older edit	Revision as of 09:05, 31 August 2022 (view source) Admin (talk \| contribs) m (1 revision imported) Newer edit →
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